Default Settings

        public Settings()
        {
            ClockFrequency = 1;
            OutputPath = "c:\\rhdl_out";
            InterfaceSourcePath = "c:\\hdl\\pico";
            XilinxToolsPath = "c:\\Xilinx\\10.1\\ISE\\bin\\nt";
            XilinxChip = "xc4vlx25-sf363-12";
            //XilinxChip = "xc4vfx12-sf363-12";
            UseClock = true;
            UseReset = true;
            UseStart = true;
            UseSDRAM = false;
            UseFIFO = false;
            SynthASIC = false;
            SynthLibaray = "tsmc035_typ";
            OptimizeSpeed = true;
            BuildHardware = false;
            RunFromXilinx = false;
            TopComponentName = "CFBase";
            OutputFormat = StructureTransformType.Verilog;
            ForceBuildHardware = false;
            SDRAMDataBits = 32;
            SDRAMAddressBits = 24;
            SDRAMBankBits = 4;
            SDRAMMaskBits = 2;
            BuildRemote = false;
            DisableCheckWellFormed = false;
            BuildServerPath = "desktop:8080";
            SkipVerilogGeneration = false;
            UseTestBus = false;
            SimulateVerilog = false;
            IcarusPath = "c:\\icarus\\bin";
            LeonardoPath = @"C:\MGC\LeoSpec\LS2008b_3\bin\win32\";
            ClockPeriodNs = 100;
        }

Last edited Sep 10, 2009 at 5:37 PM by allen248, version 1

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