Generate Hardware Scripts

In ToplevelHardware.cs the virtual GenerateHardwareScripts() method of the RapidHardware class is overridden to define a test script.

Code

        public override bool GenerateHardwareScripts()
        {
            HardwareScript oScript = HardwareScripts.NewScript("test");            
            oScript.SignalView(0, "O_COUNT");
            oScript.SignalCheck(0, "O_COUNT", "1");
            oScript.SignalView(1, "O_COUNT");
            oScript.SignalCheck(1, "O_COUNT", "2");
            oScript.SignalView(2, "O_COUNT");
            oScript.SignalCheck(2, "O_COUNT", "3");
            oScript.SignalView(3, "O_COUNT");
            oScript.SignalCheck(3, "O_COUNT", "4");
            oScript.SignalView(4, "O_COUNT");
            oScript.SignalCheck(4, "O_COUNT", "5");
            oScript.SignalView(5, "O_COUNT");
            oScript.SignalCheck(5, "O_COUNT", "6");
            oScript.SignalOut(6, "I_ENABLE", "0");
            oScript.SignalView(7, "O_COUNT");
            oScript.SignalOut(10, "I_ENABLE", "1");
            oScript.SignalView(30, "O_COUNT");
            oScript.SignalView(35, "O_COUNT");
            
            return true;
        }

Creating a new script

In this example, only one script is created. However, several scripts may be created.

The RapidHardware class includes a HardwareScripts object that manages testing. The HardwareScript class represents a test scenario.

The HardwareScripts.NewScript() method creates a new test scenario. The constructor for NewScript() inputs a script name. Note that more than one script may be defined in the GenerateHardwareScript() method.

            HardwareScript oScript = HardwareScripts.NewScript("test");            

Reporting signal view states

We have defined an "O_COUNT" signal view that reports the state of the counter output as an unsigned integer. To report the state of this signal value, the SignalView() method is called. The SignalView() method takes two parameters:
  • Time: This is a clock cycle time. In this example, 0 means before the first clock cycle, but after a reset. 2 means the second clock cycle after reset.
  • Signal View label: In this example, the O_COUNT signal will be displayed using the default unsigned format.

            oScript.SignalView(0, "O_COUNT");
...
            oScript.SignalView(2, "O_COUNT");            

Testing signal view states

The SignalCheck() method of the TestScript class has the following parameters:
  • Time - Clock cycles after reset
  • Signal View Label
  • Test Value - This parameter is a string in the DisplayFormat of the SignalView. If the SignalView's display format is hex, then this would be specified as a hex string. In this case, the display format is unsigned integer.

When the script executes, an error will be reported if the SignalCheck fails.

     oScript.SignalCheck(1, "O_COUNT", "2");
...
     oScript.SignalCheck(5, "O_COUNT", "6");

Setting Signal Sources

The SignalOut method of the TestScript Object takes the following parameters:
  • Time - Clock cycles after reset
  • Signal View Label
  • Output Value - This parameter is a string in the DisplayFormat of the SignalView. If the SignalView's display format is hex, then this would be specified as a hex string. In this case, the display format is the default, binary.

SignalOut changes the value of the SignalSource. This value is held until the next scheduled SignalOut. If the SignalSource has not yet been not assigned a SignalOut value, then the default value of the SignalSource will be applied.

     oScript.SignalOut(6, "I_ENABLE", "0");
 ...
     oScript.SignalOut(10, "I_ENABLE", "1");       

Pausing the test

The HardwareScript object includes a Pause() method that will cause the script to pause, awaiting user input. The clock time is the only parameter for pause.

     oScript.Pause(20);

Script Resets

In some cases, resetting the hardware before a script executes is not desireable. In this situation, the HardwareScript "NoReset" method may be set to true.

     oScript.NoReset = true;

Testing Options

Using the Settings of the RapidHardware, three testing options are available.
  • Verilog Test Bench
  • Live FPGA Test
  • Built in Simulation (depcricated)

Verilog test bench simulation

Rapid HDL integrates with the Icarus Verilog Simulator. If this option is selected, then:
  • A Verilog test bench file is generated.
  • The Icarus Verilog simulator is automatically invoked to simulate the hardware.
  • Errors are reported back to Rapid HDL.
  • Wave forms of the simulation may be viewed using GTKWave or other industry standard wave file viewer.

Testbench Code

The test bench generated from the script defined above is shown here.

module TEST_BENCH;


     reg CLK_I;
     reg RESET_I;
     reg I_ENABLE;
     wire [4:0] O_COUNT;


TOP top
(
     .CLK_I(CLK_I),
     .RESET_I(RESET_I),
     .I_ENABLE(I_ENABLE),
     .O_COUNT(O_COUNT)
 );

always begin
     #1 CLK_I = !CLK_I;
end

initial begin
     $dumpfile("TEST_BENCH.vcd");
     $dumpvars(0,CLK_I);
     $dumpvars(0,RESET_I);
     $dumpvars(0,I_ENABLE);
     $dumpvars(0,O_COUNT);
     I_ENABLE=1'b1;
     CLK_I=1;
     RESET_I=0;
     #2 RESET_I=1;
     #8 RESET_I=0;
     #1.9 $display("0,O_COUNT = {%b}",O_COUNT);
     #1.99999999894729E-07 if (O_COUNT != 5'b00001) $display("ERROR:0,O_COUNT = %b, expecting 5'b00001",O_COUNT);
     #1.9999998 $display("1,O_COUNT = {%b}",O_COUNT);
     #2.00000000116773E-07 if (O_COUNT != 5'b00010) $display("ERROR:1,O_COUNT = %b, expecting 5'b00010",O_COUNT);
     #1.9999998 $display("2,O_COUNT = {%b}",O_COUNT);
     #1.99999999672684E-07 if (O_COUNT != 5'b00011) $display("ERROR:2,O_COUNT = %b, expecting 5'b00011",O_COUNT);
     #1.9999998 $display("3,O_COUNT = {%b}",O_COUNT);
     #1.99999999672684E-07 if (O_COUNT != 5'b00100) $display("ERROR:3,O_COUNT = %b, expecting 5'b00100",O_COUNT);
     #1.9999998 $display("4,O_COUNT = {%b}",O_COUNT);
     #2.00000000560863E-07 if (O_COUNT != 5'b00101) $display("ERROR:4,O_COUNT = %b, expecting 5'b00101",O_COUNT);
     #1.9999998 $display("5,O_COUNT = {%b}",O_COUNT);
     #2.00000000560863E-07 if (O_COUNT != 5'b00110) $display("ERROR:5,O_COUNT = %b, expecting 5'b00110",O_COUNT);
     #0.0799997999999995 I_ENABLE = {1'b0};
     #3.92 $display("7,O_COUNT = {%b}",O_COUNT);
     #4.08 I_ENABLE = {1'b1};
     #41.92 $display("30,O_COUNT = {%b}",O_COUNT);
     #10 $display("35,O_COUNT = {%b}",O_COUNT);
     $finish();
end

endmodule

Live FPGA Test

A test script may also be executed directly on an FPGA. To operate the test, the hardware must first be synthesized using the Xilinx Toolkit, which can be time consuming.

Scripts are executed using the DoScript() method of the HardwareScript object. The results of the script are available in the RapidHDL transcript. Scripts can also be executed from the Hardware View window, which contains a "Script" button.

The Script() method inputs two parameters:
  • Resume - When resume is true, the script will pick up where it left off (i.e. continue after a pause). When resume is false, the script starts at clock cycle 0.
  • NoPause, optional - This option will cause the script to ignore pauses.

            oScript.DoScript(true);

An example of the transcript output by the test running on an FPGA is shown below:

Starting Hardware Script: test
    with reset.. 
0 : O_COUNT = {0}
0 : ERROR: expected O_COUNT = {1} != {0}

Starting Hardware Script: test
    with reset.. 
0 : O_COUNT = {1}
1 : O_COUNT = {2}
2 : O_COUNT = {3}
3 : O_COUNT = {4}
4 : O_COUNT = {5}
5 : O_COUNT = {6}
6 : set I_ENABLE = {0}
7 : O_COUNT = {6}
10 : set I_ENABLE = {1}
30 : O_COUNT = {27}
35 : O_COUNT = {5}
Completed Script: test

Built In Simulation

Rapid HDL was originally designed with a digital logic simulator. The digital logic simlation feature was intended to allow FPGA operation to be emulated without requiring logic synthesis or an actual FPGA.

However, this simulator does not work properly when several registers are involved in the simulation (there is some problem with modeling signal delays). This feature works OK for combinational logic. Therefore, some more debugging needs to take place for the simulation to be finished. You will find many artifacts from this simulator left in the RapidHDL code.

Last edited Sep 11, 2009 at 12:37 AM by allen248, version 3

Comments

No comments yet.