Settings

The process of building a bitfile is controlled by several settings variables.


The BuildHardware setting causes RapidHDL to generate a bitfile and to load it onto the FPGA. By default, if none of the generated Verilog files changes, then the bitfile synthesis will not be invoked. So, in theory, the hardware is only regenerated if the source Verilog files change. To override this behavior, the ForceBuildHardware setting may be set to true. When the ForceBuildHardware setting is true, the user will be prompted to synthesize the hardware each time the application runs.

            Settings.BuildHardware = true;
            Settings.ForceBuildHardware = false;

If we are not changing the hardware, then we may want to skip the Verilog file generation all-together.

            Settings.SkipVerilogGeneration = false;


The RunFromXilinx setting tells RapidHDL to connect SignalViews and SignalSources to the FPGA. If this setting is false, the built-in FPGA emulation simulator will be used. But be aware, the FPGA emulation system currently has bugs when more than one register is being used.

            Settings.RunFromXilinx = true;

The folder where all of the generated files will be placed is "c:\rhdl_out" by default. Synthesis will also be executed from this folder.

            Settings.OutputPath = "c:\\rhdl_out";

The permanent Verilog files that will always be used for the interface between the FPGA and the host PC are stored in the location of the InterfaceSourcePath. These files are always copied into the OutputPath before logic synthesis starts.

           Settings.InterfaceSourcePath = "c:\\hdl\\pico";

When the ISE toolchain is invoked, the toplevel component is usually going to be a permanent file used by the FPGA to host PC interface. The TopComponentName specifies which file is at the top of the hirarchy for the FPGA synthesis. Usually this component has a hierarchy that eventually includes the Verilog files generated by Rapid HDL.

            Settings.TopComponentName = "CFBase";

The path to the Xilinx tools, the FPGA type, and the OptimizeSpeed setting must be specified.

            Settings.XilinxToolsPath = "c:\\Xilinx\\10.1\\ISE\\bin\\nt";
            Settings.XilinxChip = "xc4vlx25-sf363-12";
            Settings.OptimizeSpeed = true;

If using a remote build server, the following settings should be set.


            Settings.BuildRemote = false;
            Settings.BuildServerPath = "buildserverurl.org:8080";

Xilinx Toolchain

The xilinx tool chain consists of several programs.

xst

Before calling xst, RapidHDL generates an xst project file named xst.prj containing all of the Verilog files that need to be synthesized.

xst.prj

verilog work CFBase.v
verilog work BackplaneDetector.v
verilog work CFDecoder.v
verilog work ShortFallingDelay.v
verilog work CFClockGen.v
verilog work CFCECleaner.v
verilog work CFClean.v
verilog work CFByteMode.v
verilog work CFDatabusDecoder.v
verilog work CFMemRead.v
verilog work RisingAndFallingDelay.v
verilog work CFMemWrite.v
verilog work LongDelay.v
verilog work Delay.v
verilog work CFIORead.v
verilog work CFIOWrite.v
verilog work CFAddressDecoder.v
verilog work AddressLatchDecoder.v
verilog work PulseGen.v
verilog work CFCOR.v
verilog work VccAuxFix.v
verilog work MemoryPeripherals.v
verilog work FlashROM.v
verilog work FlashWaitTimer.v
verilog work CPLDController.v
verilog work TupleDecoder.v
verilog work E12Tuple.v
verilog work CardInfo.v
verilog work IOPeripherals.v
verilog work JTAGEmulator.v
verilog work StatusAndReset.v
verilog work rhdl_pico_peripheral.v
verilog work rhdl_pico_ctl.v
verilog work SDRAMClockGen.v
verilog work mobile_sdram_ctl.v
verilog work rhdl_RegisterComponent.v
verilog work rhdl_Constant.v
verilog work rhdl_RegisterComponent2.v
verilog work rhdl_RegisterComponent3.v
verilog work rhdl_RegisterComponent4.v
verilog work rhdl_ClockSink.v
verilog work rhdl_RegisterComponent5.v
verilog work rhdl_RegisterComponent6.v
verilog work rhdl_Mux.v
verilog work rhdl_RegisterComponent7.v
verilog work rhdl_RegisterComponent8.v
verilog work rhdl_RegisterComponent9.v
verilog work rhdl_Decoder.v
verilog work rhdl_Constant2.v
verilog work rhdl_ExternalSignalInterface.v
verilog work rhdl_MainClock.v
verilog work rhdl_Constant3.v
verilog work rhdl_AndGate.v
verilog work rhdl_Not.v
verilog work rhdl_ConstantSelect.v
verilog work rhdl_HalfAdder.v
verilog work rhdl_Adder.v
verilog work rhdl_Xnor.v
verilog work rhdl_AndGate2.v
verilog work rhdl_CompareEqual.v
verilog work rhdl_OrGate.v
verilog work rhdl_Constant4.v
verilog work rhdl_RegisterComponent10.v
verilog work rhdl_UpCounter.v
verilog work rhdl_Constant5.v
verilog work rhdl_TopLevelComponent.v
verilog work rhdl_ExternalInterfaceComponent.v

Many of these files are firmware files from the folder defined by Settings.InterfaceSourcePath. Rapid HDL knows which files to include in this project file by including all files listed in InterfaceFiles.txt, which must be located in the folder defined by Settings.InterfaceSourcePath.

InterfaceFiles.txt

CFBase.v
BackplaneDetector.v
CFDecoder.v
ShortFallingDelay.v
CFClockGen.v
CFCECleaner.v
CFClean.v
CFByteMode.v
CFDatabusDecoder.v
CFMemRead.v
RisingAndFallingDelay.v
CFMemWrite.v
LongDelay.v
Delay.v
CFIORead.v
CFIOWrite.v
CFAddressDecoder.v
AddressLatchDecoder.v
PulseGen.v
CFCOR.v
VccAuxFix.v
MemoryPeripherals.v
FlashROM.v
FlashWaitTimer.v
CPLDController.v
TupleDecoder.v
E12Tuple.v
CardInfo.v
IOPeripherals.v
JTAGEmulator.v
StatusAndReset.v
CFBase-noppc.ucf
include PicoDefines.v
include RamLowLevel.v
include CFBaseLowLevel.v
include CFBaseChipScopeTaps.v
rhdl_pico_peripheral.v
rhdl_pico_ctl.v
RHDLClockGen.v
SDRAMClockGen.v
mobile_sdram_ctl.v
rhdl_pico_io.v
rhdl_pico_sdram_io.v
fifo1.v
sync_r2w.v
sync_w2r.v
fifomem1.v
rptr_empty1.v
wptr_full1.v

The options file used by xst is also generated with a .xst suffix. The prefix of this file will match the toplevel component of the design being synthesized.

CFBase.xst

run -ifn c:\rhdl_out\xst.prj
-ifmt mixed
-top CFBase
-ofn CFBase.ngc 
-ofmt NGC 
-p xc4vfx12-12-sf363
-opt_mode Speed 
-opt_level 2
-power NO
-iuc NO
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis YES
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation no
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 16
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

ngdbuild

Parameter options used for ngdbuild include:

            sParam = "-dd _ngo -nt timestamp -uc " + sUCF + " -p " + psXilinxChip + " " + psTopComponent + ".ngc " + psTopComponent + ".ngd";

map

Parameter options used for map include:

            sParam = "-p " + psXilinxChip + " -cm area -pr b -c 100 -o " + psTopComponent + "_map.ncd " + psTopComponent + ".ngd " + psTopComponent + ".pcf";

par

Parameters options used for place and route include:

            sCommand = "par";
            sParam = "-w -ol std -t 1 " + psTopComponent + "_map.ncd  " + psTopComponent + ".ncd " + psTopComponent + ".pcf";

Parameter options used for bitgen include:

            sParam = "-w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No " + psTopComponent + ".ncd";

More Information

The code that controls Xilinx Synthesis is located in XilinxTools.cs.

Last edited Sep 10, 2009 at 11:56 PM by allen248, version 3

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