module rhdl_RegisterComponent
   (ENABLE_I,
   CLK_I,
   REG_I,
   REG_O);

      input ENABLE_I;
      input CLK_I;
      input [4:0] REG_I;

      output [4:0] REG_O;





//*****  Redundant Wiring  *****


//*****  Subcomponet Declarations  *****


         reg [4:0] REG_O;

always @(posedge CLK_I)
begin
      if (ENABLE_I)
      begin
         REG_O <= REG_I;
      end
end

endmodule

Last edited Sep 9, 2009 at 9:12 PM by allen248, version 2

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