module rhdl_OrGate
   (In,
   Out);

      input [1:0] In;

      output Out;





//*****  Redundant Wiring  *****


//*****  Subcomponet Declarations  *****


         reg Out;

always @(In)
begin
   case ({In})
         2'b00 : {Out} = 1'b0;
         default : {Out} = 1'b1;
   endcase
end

endmodule

Last edited Sep 9, 2009 at 9:13 PM by allen248, version 2

Comments

No comments yet.