Mentor Graphics

Mentor Graphics is a tool used to design Integrated Circuits. Rapid HDL generates files for use with the Mentor Higher Education ASIC Design Kit. The Mentor Graphics programs used in this design toolkit include:
  • Modelsim
  • Leonardo Spectrum
  • Design Architect IC
  • IC Station
  • Calibre
  • MachTA

Targeting a design for Mentor Graphics

Designs that are built using the PadFrame base class instead of the RapidHardware base class will include the extra functionality to interact with Mentor Graphics.

Simulation with Modelsim

Modelsim is a Verilog simulator, much like Icarus Verilog. Defining a test script for the hardware design will cause a Verilog test bench to be created. Additionally, a ".do" file script for Modelsim will be generated, as shown below.

vlog -reportprogress 300 -work work {rhdl_Constant3.v}
vlog -reportprogress 300 -work work {rhdl_AndGate.v}
vlog -reportprogress 300 -work work {rhdl_OrGate.v}
vlog -reportprogress 300 -work work {rhdl_Not.v}
vlog -reportprogress 300 -work work {rhdl_ConstantSelect.v}
vlog -reportprogress 300 -work work {rhdl_Adder.v}
vlog -reportprogress 300 -work work {rhdl_Xnor.v}
vlog -reportprogress 300 -work work {rhdl_AndGate2.v}
vlog -reportprogress 300 -work work {rhdl_CompareEqual.v}
vlog -reportprogress 300 -work work {rhdl_Constant4.v}
vlog -reportprogress 300 -work work {rhdl_RegisterComponent.v}
vlog -reportprogress 300 -work work {rhdl_UpCounter.v}
vlog -reportprogress 300 -work work {rhdl_MainClock.v}
vlog -reportprogress 300 -work work {rhdl_TopLevelComponent.v}
vlog -reportprogress 300 -work work {TOP.v}
vlog -reportprogress 300 -work work {TEST_BENCH.v}
vsim -c TEST_BENCH -novopt
view wave
add wave /TEST_BENCH/top/*
run 83.9

This script will cause the test bench to be executed in Modelsim. This script can also be used for post-synthesis simulation, by simply replacing {TOP.v} with the post-synthesis Verilog file.

Logic Synthesis with Leonardo Spectrum

Leonardo Spectrum inputs Verilog files and then does logic synthesis to convert the design to a Verilog netlist of standard cells. These standard cells are then layed out on an integrated circuit.

To enable logic synthesis by Leonardo Spectrum, turn on the SynthASIC setting.

            Settings.SynthASIC = true;

The script used by Leonardo Spectrum will be generated, and then Leonardo Spectrum will be called to execute the script.

load_lib /leonardo/tsmc035_typ.syn
read {c:/rhdl_out/rhdl_Constant3.v}
read {c:/rhdl_out/rhdl_AndGate.v}
read {c:/rhdl_out/rhdl_OrGate.v}
read {c:/rhdl_out/rhdl_Not.v}
read {c:/rhdl_out/rhdl_ConstantSelect.v}
read {c:/rhdl_out/rhdl_Adder.v}
read {c:/rhdl_out/rhdl_Xnor.v}
read {c:/rhdl_out/rhdl_AndGate2.v}
read {c:/rhdl_out/rhdl_CompareEqual.v}
read {c:/rhdl_out/rhdl_Constant4.v}
read {c:/rhdl_out/rhdl_RegisterComponent.v}
read {c:/rhdl_out/rhdl_UpCounter.v}
read {c:/rhdl_out/rhdl_MainClock.v}
read {c:/rhdl_out/rhdl_TopLevelComponent.v}
read {c:/rhdl_out/TOP.v}
set_attribute -net CLK_I -name clock_cycle -value 10000
optimize -ta tsmc035_typ -effort standard -macro -area -hierarchy flatten -pass 4
report_area -cell
apply_rename_rules -ruleset VERILOG
auto_write TOP_SYNTH.v

The output of Leonardo Spectrum synthesis is a new Verilog file, TOP_SYNTH.v. This file can be used for post-layout simulation in Modelsim. It will also be used in Mentor Graphics to create a schematic for the integrated circuit.

   Insert here

Import Schematic using Design Architect IC

TOP_SYNTH.v needs to be manually imported into Design Architect IC to create a schematic. Do this following the procedure outlined in the Mentor Graphics ASIC Design Kit manual.

Layout using IC Station

Use IC Station to create a standard cell layout from the schematic. Save this component.

Padframe Verilog

Rapid HDL generates Verilog that can be used to place the design in a MOSIS 40 pin TinyChip padframe.

The pins must be associated to SignalViews and SignalSources in the ToplevelHardware class.

In TopLevelHardware.cs, the GenerateStructure() method contains these commands that define the pin placement of the power pins and the "I_ENABLE" signal source.

            AssignPinCLK(39);
            AssignPinGND(40);
            AssignPinVDD(20);
            AssignPinInput("I_ENABLE", 37);

Similarly, after defining the "O_COUNT" signal view in ConfigureSignalViews(), pins are assigned the output signal view.

            AssignPinOutput("O_COUNT", 31);

Note that OCOUNT is a signal that is 5 bits wide. Therefore, pins 31-35 will be used to output OCOUNT.

When Rapid HDL is executed, it will generate PINS.v, a Verilog netlist that is compatible with the Mentor Graphics ASIC Design Kit.

module PINS(
     CLK_I,
     RESET_I,
     I_ENABLE,
     O_COUNT
);

     input CLK_I;
     input RESET_I;
     input I_ENABLE;
     output [4:0] O_COUNT;


     wire w_clk_i;
     wire w_reset_i;
     wire w_i_enable;
     wire [4:0] w_o_count;

TOP top
(
     .CLK_I(w_clk_i),
     .RESET_I(w_reset_i),
     .I_ENABLE(w_i_enable),
     .O_COUNT(w_o_count)
 );

wire dummy39;
PadInC PIN39(
     .Pad(CLK_I),
     .DataIn(w_clk_i),
     .DataInB(dummy39)
     );
wire dummy37;
PadInC PIN37(
     .Pad(I_ENABLE),
     .DataIn(w_i_enable),
     .DataInB(dummy37)
     );

PadOut PIN31(
     .Pad(O_COUNT[0]),
     .DataOut(w_o_count[0])
     );
PadOut PIN32(
     .Pad(O_COUNT[1]),
     .DataOut(w_o_count[1])
     );
PadOut PIN33(
     .Pad(O_COUNT[2]),
     .DataOut(w_o_count[2])
     );
PadOut PIN34(
     .Pad(O_COUNT[3]),
     .DataOut(w_o_count[3])
     );
PadOut PIN35(
     .Pad(O_COUNT[4]),
     .DataOut(w_o_count[4])
     );

wire w_vdd;
fake_vdd vdd_fake(.Y(w_vdd));
PadVdd PIN20(
     .Vdd(w_vdd)
     );

wire w_gnd;
fake_gnd gnd_fake(.Y(w_gnd));
PadGnd PIN40(
     .Gnd(w_gnd)
     );

endmodule

Padframe Layout

This file can be imported using Design Architect IC to create the PadFrame schematic. Schematic driven layout in IC station can then be utilized to place the padframe and to place your design in the padframe.

There is one detail that needs to be mentioned. Design Architect IC will need to know where to find the symbol for the ToplevelHardware design, which is named TOP in the PINS.v file.

TOP top
(
     .CLK_I(w_clk_i),
     .RESET_I(w_reset_i),
     .I_ENABLE(w_i_enable),
     .O_COUNT(w_o_count)
 );

The location map file, (usually ADK.vmp) will need to be modified to include the TopLevel design. If you do not have permissions to the location map file, you can make a copy to your home directory and use it locally.

Post Layout Simulation

MachTA is a post-layout spice simulator optimized for digital logic. After a design has a layout, a post-layout spice extraction is performed using Calibre.

Rapid HDL outputs the hardware's test script in a format usable by Mach TA for post layout Spice verification. For hardware generated using MachTA, the ports for a layout extraction, and ports for a pad frame layout have the same names, so the same test can be used at both states of the design.

Rapid HDL outputs two files.

mta.do

The first file is a ".do" file and may be called from the MachTA command prompt. This file adds the signals to display and then executes a text vector file.

plot V(CLK_I)
plot V(RESET_I)
plot V(I_ENABLE)
plot V(O_COUNT[4])
plot V(O_COUNT[3])
plot V(O_COUNT[2])
plot V(O_COUNT[1])
plot V(O_COUNT[0])
run -tvend -dc mta_rom.tv

mta_rom.tv

The .tv test vector file supplies test vectors for MTA to use during post layout simulation.

CODEFILE
UNITS ns
RISE_TIME .5
FALL_TIME .5
INPUTS CLK_I,RESET_I,I_ENABLE;
OUTPUTS O_COUNT[4],O_COUNT[3],O_COUNT[2],O_COUNT[1],O_COUNT[0];
CODING(ROM)
@0 <011>XXXXX;
@50 <111>XXXXX;
@98 <111>XXXXX;
@100 <011>XXXXX;
@150 <111>XXXXX;
@198 <111>XXXXX;
@200 <011>XXXXX;
@250 <111>XXXXX;
@298 <111>XXXXX;
@300 <011>XXXXX;
@350 <111>XXXXX;
@398 <111>XXXXX;
@400 <001>XXXXX;
@450 <101>XXXXX;
@498 <101>XXXXX;
@500 <001>XXXXX;
@550 <101>XXXXX;
@598 <101>00001;
@600 <001>XXXXX;
@650 <101>XXXXX;
@698 <101>00010;
@700 <001>XXXXX;
@750 <101>XXXXX;
@798 <101>00011;
@800 <001>XXXXX;
@850 <101>XXXXX;
@898 <101>00100;
@900 <001>XXXXX;
@950 <101>XXXXX;
@998 <101>00101;
@1000 <001>XXXXX;
@1050 <101>XXXXX;
@1098 <101>00110;
@1100 <000>XXXXX;
@1150 <100>XXXXX;
@1198 <100>XXXXX;
@1200 <000>XXXXX;
@1250 <100>XXXXX;
@1298 <100>XXXXX;
@1300 <000>XXXXX;
@1350 <100>XXXXX;
@1398 <100>XXXXX;
@1400 <000>XXXXX;
@1450 <100>XXXXX;
@1498 <100>XXXXX;
@1500 <001>XXXXX;
@1550 <101>XXXXX;
@1598 <101>XXXXX;
@1600 <001>XXXXX;
@1650 <101>XXXXX;
@1698 <101>XXXXX;
@1700 <001>XXXXX;
@1750 <101>XXXXX;
@1798 <101>XXXXX;
@1800 <001>XXXXX;
@1850 <101>XXXXX;
@1898 <101>XXXXX;
@1900 <001>XXXXX;
@1950 <101>XXXXX;
@1998 <101>XXXXX;
@2000 <001>XXXXX;
@2050 <101>XXXXX;
@2098 <101>XXXXX;
@2100 <001>XXXXX;
@2150 <101>XXXXX;
@2198 <101>XXXXX;
@2200 <001>XXXXX;
@2250 <101>XXXXX;
@2298 <101>XXXXX;
@2300 <001>XXXXX;
@2350 <101>XXXXX;
@2398 <101>XXXXX;
@2400 <001>XXXXX;
@2450 <101>XXXXX;
@2498 <101>XXXXX;
@2500 <001>XXXXX;
@2550 <101>XXXXX;
@2598 <101>XXXXX;
@2600 <001>XXXXX;
@2650 <101>XXXXX;
@2698 <101>XXXXX;
@2700 <001>XXXXX;
@2750 <101>XXXXX;
@2798 <101>XXXXX;
@2800 <001>XXXXX;
@2850 <101>XXXXX;
@2898 <101>XXXXX;
@2900 <001>XXXXX;
@2950 <101>XXXXX;
@2998 <101>XXXXX;
@3000 <001>XXXXX;
@3050 <101>XXXXX;
@3098 <101>XXXXX;
@3100 <001>XXXXX;
@3150 <101>XXXXX;
@3198 <101>XXXXX;
@3200 <001>XXXXX;
@3250 <101>XXXXX;
@3298 <101>XXXXX;
@3300 <001>XXXXX;
@3350 <101>XXXXX;
@3398 <101>XXXXX;
@3400 <001>XXXXX;
@3450 <101>XXXXX;
@3498 <101>XXXXX;
@3500 <001>XXXXX;
@3550 <101>XXXXX;
@3598 <101>XXXXX;
@3600 <001>XXXXX;
@3650 <101>XXXXX;
@3698 <101>XXXXX;
@3700 <001>XXXXX;
@3750 <101>XXXXX;
@3798 <101>XXXXX;
@3800 <001>XXXXX;
@3850 <101>XXXXX;
@3898 <101>XXXXX;
@3900 <001>XXXXX;
@3950 <101>XXXXX;
@3998 <101>XXXXX;
@4000 <001>XXXXX;
@4050 <101>XXXXX;
@4098 <101>XXXXX;
@4100 <001>XXXXX;
@4150 <101>XXXXX;
END

Last edited Sep 10, 2009 at 5:16 PM by allen248, version 2

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