module rhdl_ConstantSelect
   (DATA_I,
   SEL_I,
   DATA_O);

      input [4:0] DATA_I;
      input SEL_I;

      output [4:0] DATA_O;

      wire and2_In_c;

      wire [1:0] and2_In;



//*****  Redundant Wiring  *****

         assign and2_In = {and2_In_c,DATA_I[2]};

//*****  Subcomponet Declarations  *****


rhdl_AndGate and2 (
      .In({and2_In_c,DATA_I[2]}),
      .Out({DATA_O[2]})
   );

rhdl_OrGate or0 (
      .In({SEL_I,DATA_I[0]}),
      .Out({DATA_O[0]})
   );

rhdl_AndGate and4 (
      .In({and2_In_c,DATA_I[4]}),
      .Out({DATA_O[4]})
   );

rhdl_AndGate and3 (
      .In({and2_In_c,DATA_I[3]}),
      .Out({DATA_O[3]})
   );

rhdl_AndGate and1 (
      .In({and2_In_c,DATA_I[1]}),
      .Out({DATA_O[1]})
   );

rhdl_Not not_sel (
      .In({SEL_I}),
      .Out({and2_In_c})
   );

// Component Did Not Write Any Custom Verilog

endmodule

Last edited Sep 9, 2009 at 8:11 PM by allen248, version 3

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