This project is read-only.
module rhdl_CompareEqual
   (InA,
   InB,
   Out);

      input [4:0] InA;
      input [4:0] InB;

      output Out;

      wire [4:0] and_all_In;

      wire xnor3_Output;
      wire xnor0_Output;
      wire xnor1_Output;



//*****  Redundant Wiring  *****

         assign xnor3_Output = {and_all_In[3]};
         assign xnor0_Output = {and_all_In[0]};
         assign xnor1_Output = {and_all_In[1]};

//*****  Subcomponet Declarations  *****


rhdl_Xnor xnor3 (
      .Input({InB[3],InA[3]}),
      .Output({and_all_In[3]})
   );

rhdl_Xnor xnor0 (
      .Input({InB[0],InA[0]}),
      .Output({and_all_In[0]})
   );

rhdl_Xnor xnor1 (
      .Input({InB[1],InA[1]}),
      .Output({and_all_In[1]})
   );

rhdl_AndGate2 and_all (
      .In({and_all_In}),
      .Out({Out})
   );

rhdl_Xnor xnor4 (
      .Input({InB[4],InA[4]}),
      .Output({and_all_In[4]})
   );

rhdl_Xnor xnor2 (
      .Input({InB[2],InA[2]}),
      .Output({and_all_In[2]})
   );

// Component Did Not Write Any Custom Verilog

endmodule

Last edited Sep 9, 2009 at 9:13 PM by allen248, version 2

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