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Basic Foundational Objects


A component contains the logic definition and the inputs and outputs of a hardware component. A component maps directly to a Verilog module. Components are organized in a hierarchy, and may contain other components. A component must have a top level component.

Think of a component as you might think of electrical parts placed on a breadboard. Components each have their own function and specification. Components are wired together. Components can be organized in hierarchies of components.


A node represents a connection point in a component. Each node has a parent component. There are 3 types of nodes:
  • Source Node - The source of a signal originates at this node. The node's parent component has active logic that will change the output state of this node.
  • Sink Node - This node consumes a signal. The node's parent component uses the signal input state of this node.
  • Passthrough Node - This node is merely a connection point on the route between other nodes. The node's parent component does not directly change the state of this node, nor does the parent component use the state of this node.


A node vector is a single dimensional array of nodes. A node vector is basically a data bus. All nodes in a node vector must be of the same type, i.e. Source, Sink, or Passthrough.


A net is a collection of connected nodes. A net should contain a single source node, and at least one sink node. A net may also have passthrough nodes. Nodes in a net typically have different parent components. A sink node in a net must be seperated from source nodes in the net by at least one register.

TruthTable Component

The Truth Table component inherits from the component class. It is the simplest way to implement combinational digital logic. It has sink nodes as inputs and source nodes as outputs.

Override the GenerateTruthTable function to specify the logical input and output mapping of the component.

Register Component

The register component is implemented as D-Flip Flops. Input nodes are latched on either the rising or the falling edge of the clock. Registers must separate combination logic for good RTL design.


The toplevel component has no parent component and serves as the root node of the component hierarchy. When the hardware is synthesized, the toplevel component provides the inputs and outputs of the final component. The toplevel component also includes a main clock object and a reset node.

Signal View

A signal view is a special node vector that can be connected to any node, including the inputs of the toplevel component. A singal view is used after the hardware has been synthesized and is running on the FPGA. Software running on a host PC may pause the FGPA and read the signal state of the signal view. Signal views are also used in test scripts to view the internal state of the simulated hardware.

Signal Source

A signal source is a special node vector that can be connected to the input nodes of the toplevel component. After the hardware has been synthesized and is running on the FPGA, signal sources may be controlled by software running on host PC to change the inputs of the FGPA. Signal sources are also used in test scripts to change the inputs of simulated hardware.


This is the highest level component of a rapid hardware design. This componet provides access to all methods related to testing and using the hardware.

Last edited Sep 9, 2009 at 6:28 PM by allen248, version 2


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